Our patented technologies include:
- ZWLCT® – Zero Width Laser Cutting Technology
- QLWT® – Quartz Laser Welding Technology
- SSL® – Solid State Lapping
- FWLDT® – Fantom Wafer Laser Dicing Technology
Fonon Technologies was established in 1991 as an R&D company by a group of high-level scientists and engineers as a result of research and development in three major worldwide patented technologies in the hi-tech industry: Fiber Laser Material Processing Technology, Zero Width Laser Cutting Technology®, Solid State Lapping® (SSL), and Quartz Laser Welding Technology® (QLWT).
Laser Photonics continues to develop and manufacture state-of-the-art equipment and Technologies for glass scribing, cutting and breaking, wafer dicing, ITO ablation, Direct Patterning, Direct Laser Component Marking, Fiber Laser Material Processing solutions, UID, Portable Laser Systems, and more to our customers in the FPD, Semiconductor and Electronics industries throughout the world.
Laser Photonics was the first in the world to develop a laser scribing system with simultaneous Laser Scribe and Break capabilities for singulation of Flat Panel Display panels specifically for Generation 6 and 8 Glass panels.
Wafers have the highest value at the dicing stage and the primary focus of FWLDT is to increase the number of dies, yield per wafer, and to maximize throughput while minimizing the HAZ specifically for “power hungry” RF micro devices and low-K wafer substrates.
Laser Photonics System is applicable for dicing of assorted semiconductor materials such as silicon (Si), gallium arsenide (GaAs), germanium (Ge), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN), gallium phosphide (GaP), other compound materials, as well as low-k and multi-layer composite materials.
Significant Advantages of Dicing and Separation Technology:
The possibility of a cut with zero or 20 micron narrow width (application specific) allows wafer layout designers to reduce the width of the spacing between adjacent die on a wafer. The spacing is normally reserved to allow for the width of the saw used to cut the wafer. A reduction of the spacing width will result in an increase of the real estate available for die, which will result in a significant reduction of the cost per die.